1. Field of the Invention
The present invention relates to a driving circuit for a liquid crystal display (LCD) device, and more particularly, to an analog buffer circuit for an LCD device.
2. Discussion of the Related Art
As demand for various display devices increases, development of various flat display devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, electroluminescent display (ELD) devices, and vacuum fluorescent display (VFD) devices, has begun. These flat display devices are commonly used because of their thin profile, light weight, and low power consumption. For example, the LCD devices are commonly used in notebook computer, computer monitors, and televisions.
In general, an LCD device includes an LCD panel displaying images and an external driving circuit supplying driving signals to the LCD panel. The LCD panel includes first and second transparent substrates, such as glass substrates, bonded to each other and having a predetermined interval therebetween, and a liquid crystal material injected between the first and second substrates. The first substrate includes a plurality of gate and data lines crossing each other to define a plurality of pixel regions, a plurality of pixel electrodes disposed within each of the pixel regions, and a plurality of thin film transistors disposed at crossing portions of the gate and data lines to supply video signals transmitted along the data lines to respective ones of the pixel electrodes according to gate signals transmitted along the gate lines. The second substrate includes a black matrix layer, a color filter layer, and a common electrode. Accordingly, as turn-ON signals are sequentially supplied to the gate lines, the data signals are transmitted to the pixel electrodes of the corresponding data line, thereby displaying images.
In addition, a backlight device is provided at a rear side of the two substrates, and uses a cold cathode fluorescent lamp (CCFL) as a light source. Accordingly, luminance is inversely proportional to a lifespan of the CCFL. When driving the backlight device at a high voltage for increased luminance, the lifespan of the backlight device decreases. Accordingly, increasing the lifespan of the backlight device may be accomplished by driving the backlight device at a low voltage. However, it is difficult to improve the luminance of the backlight device. Thus, a backlight device having both a long lifespan and high luminance is required. One solution is to momentarily supply a high voltage to the lamp of the backlight device when driving the LCD panel. Accordingly, the amount of current for the lamp of the backlight device is changed according to the image displayed on the LCD panel. For example, during a normally white mode wherein incident light is prevented from being transmitted by the LCD panel by aligning liquid crystal molecules along an electric field direction, the power consumption of the LCD panel decreases as the number of active pixels on the LCD panel increases. Conversely, the power consumption of the LCD panel increases as the number of dark (inactive) pixels on the LCD panel increases. Accordingly, it is possible to control the current value for the lamp on the basis of the power consumption for the LCD panel. Thus, an additional circuit is required for detecting the current consumed by the LCD panel, wherein changing the detected current is necessary for meeting a variable range of luminance control signals of the inverter for driving the backlight device.
FIG. 1A is a schematic plan view of a-Si TFT-LCD device according to the related art, and FIG. 1B is a schematic plan view of a polysilicon TFT-LCD device according to the related art. In FIG. 1A, an amorphous silicon thin film transistor LCD (a-Si TFT-LCD) device includes a thin film transistor (TFT) array 3 formed on a first substrate 1, data and gate drivers 6 and 8 for driving the TFT array 3, and a printed circuit board (PCB) substrate 4 interconnecting the TFT array 3 with the data and gate drivers 6 and 8. In the a-Si TFT-LCD device, the data and gate drivers 6 and 8 are formed at an exterior of the first substrate 1 due to the low field mobility of the a-Si TFT-LCD device, whereby a total number of signal lines for electrical connection increases.
In FIG. 1B, a polysilicon thin film transistor LCD (poly-Si TFT-LCD) device includes a TFT array 5 on a substrate 2, and data and gate drivers 7 and 9 for driving the TFT array 5. The poly-Si TFT-LCD device has a driving circuit for the data and gate drivers 7 and 9 within the substrate 2, thereby decreasing a total number of signal lines for electrical connection and improving reliability and yield. In addition, since the poly-Si TFT has a high field mobility and a smaller size than the a-Si TFT, the poly-Si TFT functions as a pixel switch, thereby improving aperture ratio of the a-Si TFT-LCD device.
FIG. 2 is a schematic block diagram of a driving circuit for an LCD device according to the related art. In FIG. 2, an LCD device includes an LCD panel 21, a driving circuit part 22, and a backlight device 28. The LCD panel 21 includes a plurality of pixel regions arranged in a matrix-type configuration, wherein each pixel region is defined by a crossing of a gate line G and a data line D. The driving circuit part 22 supplies driving and data signals to the LCD panel 21, and the backlight device 28 provides light to the LCD panel 21.
The driving circuit part 22 includes a data driver 21b, a gate driver 21a, a timing controller 23, a power supply part 24, a gamma reference voltage part 25, an AC/DC converter 26, and an lamp driving part 29. Accordingly, the data driver 21b inputs a data signal to each of the data lines D of the LCD panel 21, and the gate driver 21a supplies a gate driving pulse to each of the gate lines G of the LCD panel 21. Then, the timing controller 23 receives display data R/G/B, vertical and horizontal synchronous signals Vsync and Hsync, a clock signal DCLK, and control signals from a driving system 27 of the LCD panel 21. Accordingly, the timing controller 23 formats the display data R/G/B, the clock signal DCLK, and the control signals having a timing suitable for restoring an image by the gate driver 21a and the data driver 21b of the LCD panel 21. In addition, the gamma reference voltage part 25 receives power from the power supply part 24 to provide a reference voltage required when digital data input from the data driver 21b is converted into analog data. The AC/DC converter 26 outputs a constant voltage VDD, a gate high voltage VGH, a gate low voltage VGL, a reference voltage Vref, and a common voltage Vcom for the LCD panel 1 by using a voltage output from the power supply part 24. Accordingly, the lamp driving part 29 drives the backlight device 28.
Operation of the LCD device includes the timing controller 23 receiving the display data R/G/B, the vertical and horizontal synchronous signals Vsync and Hsync, the clock signal DCLK, and the control signals from the driving system 27 of the LCD panel 21, and providing the display data R/G/B, the clock signal DCLK, and the control signals formatted having the timing suitable for restoring the image by the data driver 21b and the gate driver 21a of the LCD panel 21. For example, the gate driver 21a supplies the gate driving pulse to each of the gate lines G of the LCD panel 21, and the synchronous data driver 21b inputs the data signals to each of the data lines D of the LCD panel 21, thereby displaying the input image. At this time, the backlight device 28 provides constant brightness without relation to luminance of the input image signals.
FIG. 3 is a schematic block diagram of a data driver in FIG. 2 according to the related art. In FIG. 3, the data driver 21b (in FIG. 2) includes a shift register 31, a sampling latch 32, a holding latch 33, a D/A (digital/analog) converter 34, and an output buffer 35. The shift register 31 shifts a horizontal synchronous signal pulse Hsync through a source pulse clock HCLK, and outputs a latch enable clock to the sampling latch 32. Subsequently, the sampling latch 32 samples the R, G, and B digital data for each column line in accordance with the latch enable clock output from the shift register 31, and then latches the sampled R, G, and B data. Next, the holding latch 33 latches the R, G, and B data latched by the sampling latch 32 through a load signal LD, and the D/A converter 34 converts the R, G, and B digital data latched by the holding latch 33 into analog signals. Then, the amplifier 35 amplifies the R, G, and B data converted into the analog signals at a certain width, and outputs the amplified R, G, and B data to each of the data lines D (in FIG. 2) of the LCD panel 21 (in FIG. 2). Accordingly, the data driver 21b (in FIG. 2) samples and holds the R, G, and B digital data during one horizontal period, converts them into analog data, and amplifies the converted analog data at a certain width. If the holding latch 33 holds the R, G, and B data to be applied to an nth numbered column line, then the sampling latch 32 samples the R, G, and B data to be applied to an (n+1)th numbered column line.
FIG. 4 is a schematic block diagram of a gate driver in FIG. 2 according to the related art. In FIG. 4, the gate driver 21a (in FIG. 2) includes a shift register 41, a level shifter 42, and an output buffer 43. The shift register 41 shifts the vertical synchronous signal pulse Vsync through a gate pulse clock VCLK, thereby sequentially enabling scanning lines. Subsequently, the level shifter 42 sequentially level-shifts signals applied to the scanning lines, and then outputs the level-shifted signals to the output buffer 43. Accordingly, the plurality of scanning lines connected with the output buffer 43 are sequentially enabled.
FIG. 5 is a schematic circuit diagram of an analog buffer circuit for an LCD device according to the related art. In FIG.5, an analog buffer circuit for an LCD device includes an input terminal, an output terminal, a capacitor 44, an inverter 45, a first reset switch 46, a second reset switch 47, and a feedback switch 48. The capacitor 44 and the inverter 45 are connected in series between the input terminal and the output terminal, and the first reset switch 46 is connected to a first node P1 between the input terminal and the capacitor 44 to reset the capacitor 44. In addition, the second reset switch 47 is connected between a second node P2 and a third node P3 to reset the inverter 45, wherein the second node P2 is connected between the capacitor 44 and the inverter 45, and the third node P3 is connected between the inverter 45 and the output terminal. Furthermore, the feedback switch 48 is connected between the second node P2 and the third node P3.
Operation of the analog buffer circuit for the LCD device includes initialization on an output terminal of the inverter 45 such that the first and second reset switches 46 and 47 are closed, whereby input and output of the inverter 45 is initialized to an intermediate potential of a power voltage. Subsequently, an analog data voltage and a video signal are input to an external DAC (not shown) from the input terminal. Then, a voltage corresponding to a difference between the initialized intermediate voltage and an input voltage is stored in the capacitor 44. When the feedback switch 48 is closed, the analog data voltage input to the input terminal is monitored through the inverter 45 and the output terminal. Accordingly, the analog buffer circuit simply uses the inverter 45, thereby decreasing the power consumption, as compared with that of an analog buffer circuit according to the related that uses an OP lamp.
However, the analog buffer circuit according to the related art has the following disadvantages. First, although the input voltage is applied to the output line, the inverter of the analog buffer circuit, as shown in FIG. 5, maintains the intermediate voltage, thereby increasing the power consumption due to standby current. In addition to the amplifier for the analog buffer function, an additional D/A converter and an analog buffer are required. Furthermore, the data output through the output terminal, as shown in FIG. 6, is unstable due to oscillation.